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[solved] How to enable Hyper-Threading on a Pentium4?
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schwarzygesetzlos
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PostPosted: Wed May 13, 2020 5:17 pm    Post subject: [solved] How to enable Hyper-Threading on a Pentium4? Reply with quote

Howdy ye olde x86 dudes!

Got a problem with my 'new' Pentium4 box (XPC FS51 v2.0). According to cpuinfo it supports Hyper Threading, I also enabled SMP in kernel, but still I get only 1 logical CPU core...

Code:
 # dmesg | grep -i smp
[    0.000000] Linux version 5.7.0-rc5-Pentium4 (root@supah) (gcc version 9.3.0 (Gentoo 9.3.0 p2), GNU ld (Gentoo 2.34 p1) 2.34.0) #2 SMP Mon May 11 18:35:32 CEST 2020
[    0.019368] found SMP MP-table at [mem 0x000f54c0-0x000f54cf]
[    0.066241] Using ACPI (MADT) for SMP configuration information
[    0.066252] smpboot: Allowing 2 CPUs, 1 hotplug CPUs
[    0.548533] smpboot: CPU0: Intel(R) Pentium(R) 4 CPU 2.80GHz (family: 0xf, model: 0x2, stepping: 0x7)
[    0.550487] smp: Bringing up secondary CPUs ...
[    0.550575] smp: Brought up 1 node, 1 CPU
[    0.550652] smpboot: Max logical packages: 2
[    0.551337] smpboot: Total of 1 processors activated (5595.80 BogoMIPS)

 # cat /proc/cpuinfo
processor   : 0
vendor_id   : GenuineIntel
cpu family   : 15
model      : 2
model name   : Intel(R) Pentium(R) 4 CPU 2.80GHz
stepping   : 7
microcode   : 0x33
cpu MHz      : 2796.322
cache size   : 512 KB
physical id   : 0
siblings   : 1
core id      : 0
cpu cores   : 1
apicid      : 0
initial apicid   : 0
fdiv_bug   : no
f00f_bug   : no
coma_bug   : no
fpu      : yes
fpu_exception   : yes
cpuid level   : 2
wp      : yes
flags      : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pebs bts cpuid cid xtpr
bugs      : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs itlb_multihit
bogomips   : 5594.67
clflush size   : 64
cache_alignment   : 128
address sizes   : 36 bits physical, 32 bits virtual

I even disabled Spectre etc. mitigations via mitigations=off mds=off to check if that would be the problem. But still only 1 core enabled. :cry:
Full kernel .config: https://pastebin.com/HT9mAzXd
Full dmesg: https://pastebin.com/ZWKaVEe2

The Board is a FS51 v2.0 and claims to support Hyper-Threading (http://www.shuttle.eu/_archive/older/en/ss51g_faq.htm#infofaq). Bios is latest FS51SB0L.

What am I missing here?
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Last edited by schwarzygesetzlos on Sun May 24, 2020 2:23 pm; edited 2 times in total
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NeddySeagoon
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PostPosted: Wed May 13, 2020 5:58 pm    Post subject: Reply with quote

schwarzygesetzlos,


The
Code:
Pentium(R) 4 CPU 2.80GHz (family: 0xf, model: 0x2, stepping: 0x7)
shows its a Northwood CPU.

Wikipedia lists two 2.8GHz varieties.
The links into the Intel ark both show # of Cores 1, # of Threads 1.
That makes it a pre Hyperthreading P4.

If that's correct, its a feature, not a problem. :)
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schwarzygesetzlos
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PostPosted: Wed May 13, 2020 6:30 pm    Post subject: Reply with quote

Hmm... But it does list Hyper-Threading support in its' flags:
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pebs bts cpuid cid xtpr
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PostPosted: Wed May 13, 2020 7:38 pm    Post subject: Reply with quote

@schwarzygesetzlos: there are many different variants of the Pentium 4 processor. Some support hyperthreading, some not:
  1. https://ark.intel.com/content/www/us/en/ark/products/27452/intel-pentium-4-processor-511-1m-cache-2-80-ghz-533-mhz-fsb.html
  2. https://ark.intel.com/content/www/us/en/ark/products/27461/intel-pentium-4-processor-521-supporting-ht-technology-1m-cache-2-80-ghz-800-mhz-fsb.html
The second one supports hyperhreading, the first one not.

Quote:
But it does list Hyper-Threading support in its' flags:

We had a couple of threads where it turned out that the flag ht is sometimes unreliable. You can't trust it.

Please look at the output of 'cpuid' (package sys-apps/cpuid). In section 'feature information (1/edx)'. Is there's a line about hyperthreading?
Code:
hyper-threading / multi-core supported = false

Is it true or false?
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Ant P.
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PostPosted: Thu May 14, 2020 12:39 am    Post subject: Reply with quote

CPU flags are not the source of truth on Intel CPUs, they only indicate what the silicon is capable of. To actually *use* those features requires the correct microcode, which is heavily DRMed to stop users getting features they didn't pay for.
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schwarzygesetzlos
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PostPosted: Thu May 14, 2020 9:50 am    Post subject: Reply with quote

@NeddySeagoon, mike155, Ant P. thanks for your input!

I see... Don't know yet what exact model it is. Is there a way to get the sSpec Number in software, e.g. if it's a SL7EY? If not I guess there is only one way to find out. 8O
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PostPosted: Thu May 14, 2020 7:45 pm    Post subject: Reply with quote

schwarzygesetzlos,

emerge cpuid looks promising.
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schwarzygesetzlos
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PostPosted: Sun May 17, 2020 4:52 pm    Post subject: Reply with quote

Unfortunately cpuid also does not reveal the eSpec number.
Code:
 # cpuid -i
CPU 0:
   vendor_id = "GenuineIntel"
   version information (1/eax):
      processor type  = primary processor (0)
      family          = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
      model           = 0x2 (2)
      stepping id     = 0x7 (7)
      extended family = 0x0 (0)
      extended model  = 0x0 (0)
      (simple synth)  = Intel Pentium 4 (Northwood C1) / Xeon (Prestonia C1) / Mobile Pentium 4 Processor-M (Northwood C1) / Celeron 478-Pin (Northwood C1) / Mobile Celeron (Northwood C1), .13um
   miscellaneous (1/ebx):
      process local APIC physical ID = 0x0 (0)
      cpu count                      = 0x1 (1)
      CLFLUSH line size              = 0x8 (8)
      brand index                    = 0x9 (9)
   brand id = 0x09 (9): Intel Pentium 4, .13um
   feature information (1/edx):
      x87 FPU on chip                        = true
      VME: virtual-8086 mode enhancement     = true
      DE: debugging extensions               = true
      PSE: page size extensions              = true
      TSC: time stamp counter                = true
      RDMSR and WRMSR support                = true
      PAE: physical address extensions       = true
      MCE: machine check exception           = true
      CMPXCHG8B inst.                        = true
      APIC on chip                           = true
      SYSENTER and SYSEXIT                   = true
      MTRR: memory type range registers      = true
      PTE global bit                         = true
      MCA: machine check architecture        = true
      CMOV: conditional move/compare instr   = true
      PAT: page attribute table              = true
      PSE-36: page size extension            = true
      PSN: processor serial number           = false
      CLFLUSH instruction                    = true
      DS: debug store                        = true
      ACPI: thermal monitor and clock ctrl   = true
      MMX Technology                         = true
      FXSAVE/FXRSTOR                         = true
      SSE extensions                         = true
      SSE2 extensions                        = true
      SS: self snoop                         = true
      hyper-threading / multi-core supported = true
      TM: therm. monitor                     = true
      IA64                                   = false
      PBE: pending break event               = true
   feature information (1/ecx):
      PNI/SSE3: Prescott New Instructions     = false
      PCLMULDQ instruction                    = false
      DTES64: 64-bit debug store              = false
      MONITOR/MWAIT                           = false
      CPL-qualified debug store               = false
      VMX: virtual machine extensions         = false
      SMX: safer mode extensions              = false
      Enhanced Intel SpeedStep Technology     = false
      TM2: thermal monitor 2                  = false
      SSSE3 extensions                        = false
      context ID: adaptive or shared L1 data  = true
      SDBG: IA32_DEBUG_INTERFACE              = false
      FMA instruction                         = false
      CMPXCHG16B instruction                  = false
      xTPR disable                            = true
      PDCM: perfmon and debug                 = false
      PCID: process context identifiers       = false
      DCA: direct cache access                = false
      SSE4.1 extensions                       = false
      SSE4.2 extensions                       = false
      x2APIC: extended xAPIC support          = false
      MOVBE instruction                       = false
      POPCNT instruction                      = false
      time stamp counter deadline             = false
      AES instruction                         = false
      XSAVE/XSTOR states                      = false
      OS-enabled XSAVE/XSTOR                  = false
      AVX: advanced vector extensions         = false
      F16C half-precision convert instruction = false
      RDRAND instruction                      = false
      hypervisor guest status                 = false
   cache and TLB information (2):
      0x51: instruction TLB: 4K & 2M/4M pages, 128 entries
      0x5b: data TLB: 4K & 4M pages, 64 entries
      0x66: L1 data cache: 8K, 4-way, 64 byte lines
      0x40: No L3 cache
      0x70: Trace cache: 12K-uop, 8-way
      0x7b: L2 cache: 512K, 8-way, sectored, 64 byte lines
   extended feature flags (0x80000001/edx):
      SYSCALL and SYSRET instructions        = false
      execution disable                      = false
      1-GB large page support                = false
      RDTSCP                                 = false
      64-bit extensions technology available = false
   Intel feature flags (0x80000001/ecx):
      LAHF/SAHF supported in 64-bit mode     = false
      LZCNT advanced bit manipulation        = false
      3DNow! PREFETCH/PREFETCHW instructions = false
   brand = "              Intel(R) Pentium(R) 4 CPU 2.80GHz"
   (multi-processing synth): hyper-threaded (t=2)
   (multi-processing method): Intel leaf 1
   (synth) = Intel Pentium 4 (Northwood C1), .13um

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wjb
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PostPosted: Sun May 17, 2020 5:44 pm    Post subject: Reply with quote

For a P4, hyper threading is almost certainly a BIOS setting. e.g. in Phoenix Award BIOS, it's under Advanced BIOS Features.
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schwarzygesetzlos
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PostPosted: Sun May 24, 2020 2:23 pm    Post subject: Reply with quote

Finally I had the leisure to open the case and check the CPU itself. It's a SL6HL, which is not listed among the Pentium 4 HT ones on the wikipedia page. So the riddle is solved now. ;-)
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